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FEATURES Optimized for Fiber Optic Photodiode Interfacing Eight Full Decades of Range Law Conformance 0.1 dB from 1 nA to 1 mA Single-Supply Operation (3.0 V- 5.5 V) Complete and Temperature Stable Accurate Laser-Trimmed Scaling: Logarithmic Slope of 10 mV/dB (at VLOG Pin) Basic Logarithmic Intercept at 100 pA Easy Adjustment of Slope and Intercept Output Bandwidth of 10 MHz, 15 V/ s Slew Rate 1-, 2-, or 3-Pole Low-Pass Filtering at Output Miniature 14-Lead Package (TSSOP) Low Power: ~4.5 mA Quiescent Current (Enabled) APPLICATIONS High Accuracy Optical Power Measurement Wide Range Baseband Log Compression Versatile Detector for APC Loops
160 dB Range (100 pA -10 mA) Logarithmic Converter AD8304
FUNCTIONAL BLOCK DIAGRAM
VPS2
10
PWDN
2
VPS1
12
AD8304
PDB VPDB
6 3
BIAS ~10k
VREF 0.5V
7 VREF
VSUM INPT TEMPERATURE COMPENSATION 5k
8 VLOG 9 BFIN 13 BFNG
IPD
4
VSUM 5
1
14
11
VNEG
ACOM
VOUT
PRODUCT DESCRIPTION
The AD8304 is a monolithic logarithmic detector optimized for the measurement of low frequency signal power in fiber optic systems. It uses an advanced translinear technique to provide an exceptionally large dynamic range in a versatile and easily used form. Its wide measurement range and accuracy are achieved using proprietary design techniques and precise laser trimming. In most applications only a single positive supply, VP, of 5 V will be required, but 3.0 V to 5.5 V can be used, and certain applications benefit from the added use of a negative supply, VN. When using low supply voltages, the log slope is readily altered to fit the available span. The low quiescent current and chip disable features facilitate use in battery-operated applications. The input current, IPD, flows in the collector of an optimally scaled NPN transistor, connected in a feedback path around a low offset JFET amplifier. The current-summing input node operates at a constant voltage, independent of current, with a default value of 0.5 V; this may be adjusted over a wide range, including ground or below, using an optional negative supply. An adaptive biasing scheme is provided for reducing the dark current at very low light input levels. The voltage at Pin VPDB applies approximately 0.1 V across the diode for IPD = 100 pA, rising linearly with current to 2.0 V of net bias at IPD = 10 mA. The input pin INPT is flanked by the guard pins VSUM that track the voltage at the summing node to minimize leakage.
The default value of the logarithmic slope at the output VLOG is accurately scaled to 10 mV/dB (200 mV/decade). The resistance at this output is laser-trimmed to 5 k, allowing the slope to be lowered by shunting it with an external resistance; the addition of a capacitor at this pin provides a simple low-pass filter. The intermediate voltage VLOG is buffered in an output stage that can swing to within about 100 mV of ground (or VN) and the positive supply, VP, and provides a peak current drive capacity of 20 mA. The slope can be increased using the buffer and a pair of external feedback resistors. An accurate voltage reference of 2 V is also provided to facilitate the repositioning of the intercept. Many operational modes are possible. For example, low-pass filters of up to three poles may be implemented, to reduce the output noise at low input currents. The buffer may also serve as a comparator, with or without hysteresis, using the 2 V reference, for example, in alarm applications. The incremental bandwidth of a translinear logarithmic amplifier inherently diminishes for small input currents. At the 1 nA level, the AD8304's bandwidth is about 2 kHz, but this increases in proportion to IPD up to a maximum value of 10 MHz. The AD8304 is available in a 14-lead TSSOP package and specified for operation from -40C to +85C.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AD8304-SPECIFICATIONS (V = 5 V, V = 0 V, T = 25 C, unless otherwise noted.)
P N A
Parameter INPUT INTERFACE Specified Current Range Input Node Voltage Temperature Drift Input Guard Offset Voltage PHOTODIODE BIAS Minimum Value Transresistance
2
Conditions Pin 4, INPT; Pin 3 and Pin 5, VSUM Flows toward INPT Pin Internally preset; may be altered -40C < TA < +85C VIN - VSUM Established between Pin 6, VPDB, and Pin 4 IPD = 100 pA Pin 8, VLOG Laser-trimmed at 25C 0C < TA < 70C Laser-trimmed at 25C 0C < TA < 70C 10 nA < IPD < 1 mA, Peak Error 1 nA < IPD < 1 mA, Peak Error Limited by VN = 0 V Laser-trimmed at 25C Pin 7, VREF Laser-trimmed at 25C -40C < TA < +85C Pin 9, BFIN; Pin 13, BFNG; Pin 11, VOUT
Min1 100 0.46 -20 70
Typ
Max1
Unit pA mA V mV/C mV mV mV/mA
0.5 0.02
10 0.54 +20
100 200 200 100 0.05 0.1 1.6 0.1 5 2 2 204 207 140 175 0.25 0.7
LOGARITHMIC OUTPUT Slope Intercept Law Conformance Error Maximum Output Voltage Minimum Output Voltage Output Resistance REFERENCE OUTPUT Voltage WRT Ground Output Resistance OUTPUT BUFFER Input Offset Voltage Input Bias Current Incremental Input Resistance Output Range Output Resistance Wide-Band Noise3 Small Signal Bandwidth3 Slew Rate POWER-DOWN INPUT Logic Level, HI State Logic Level, LO State POWER SUPPLY Positive Supply Voltage Quiescent Current In Disabled State Negative Supply Voltage4
196 194 60 35
4.95 1.98 1.92
5.05 2.02 2.08
mV/dec mV/dec pA pA dB dB V V k V V mV A M V V/Hz MHz V/s V V V mA A V
-20 Flowing out of Pin 9 or Pin 13 RL = 1 k to ground IPD > 1 A (see Typical Performance Characteristics) IPD > 1 A (see Typical Performance Characteristics) 0.2 V to 4.8 V output swing Pin 2, PWDN -40C < TA < +85C, 2.7 V < VP < 5.5 V -40C < TA < +85C, 2.7 V < VP < 5.5 V Pin 10 and Pin 12, VPS1 and VPS2; Pin 1, VNEG 3.0 5 4.5 60 0 2 0.4 35 VP - 0.1 0.5 1 10 15
+20
1 5.5 5.3 -5.5
|1VP -VN| < 8V
NOTES 1 Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values. 2 This bias is internally arranged to track the input voltage at INPT; it is not specified relative to ground. 3 Output Noise and Incremental Bandwidth are functions of Input Current; see Typical Performance Characteristics. 4 Optional Specifications subject to change without notice.
-2-
REV. A
AD8304
ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS
Supply Voltage VP - VN . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 270 mW JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C/W Maximum Junction Temperature . . . . . . . . . . . . . . . . 125C Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Pin No. Mnemonic Function 1 VNEG Optional Negative Supply, VN. This pin is usually grounded; for details of usage, see Applications section. Power-Down Control Input. Device is active when PWDN is taken LOW. Guard Pins. Used to shield the INPT current line. Photodiode Current Input. Usually connected to photodiode anode (the photo current flows toward INPT). Photodiode Biaser Output. May be connected to photodiode cathode to provide adaptive bias control. Voltage Reference Output of 2 V Output of the Logarithmic Front-End Processor; ROUT = 5 k to ground. Buffer Amplifier Noninverting Input (High Impedance) Positive Supply, VP (3.0 V to 5.5 V) Buffer Output; Low Impedance Positive Supply, VP (3.0 V to 5.5 V) Buffer Amplifier Inverting Input Analog Ground
2 3, 5 4
PWDN VSUM INPT
6
PIN CONFIGURATION
VNEG 1 PWDN 2 VSUM 3 INPT 4
14 13
VPDB
ACOM BFNG VPS1
7 8 9 10 11 12 13 14
VREF VLOG BFIN VPS2 VOUT VPS1 BFNG ACOM
AD8304
12
TOP VIEW 11 VOUT (Not to Scale) 10 VPS2 VSUM 5 VPDB 6 VREF 7
9 8
BFIN VLOG
ORDERING GUIDE
Model AD8304ARU AD8304ARU-REEL AD8304ARU-REEL7 AD8304-EVAL
Temperature Range -40C to +85C
Package Description Tube, 14-Lead TSSOP 13" Tape and Reel 7" Tape and Reel Evaluation Board
Package Option RU-14
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8304 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
AD8304-Typical Performance Characteristics
(VP = 5 V, VN = 0 V, TA = 25 C, unless otherwise noted.)
1.6 1.4 1.2 1.0 -40 C +25 C +85 C 0C +70 C TA = -40 C, +25 C, +85 C VN = -0.5V
0.510 TA = -40 C, +25 C, +85 C 0.508
VLOG - V
0.8 0.6 0.4
VSUM - V
0.506
0.504
-40 C +25 C
0.502
0.2 0 100p
+85 C
1n
10n
100n
1 10 INPUT - A
100
1m
10m
0.500 100p
1n
10n
100n
1 10 INPUT - A
100
1m
10m
TPC 1. VLOG vs. IPD
TPC 4. VSUM vs. IPD
2.0 1.5 1.0 0.5 0 -0.5 +85 C +70 C -1.0 -1.5 -2.0 100p TA = -40 C, +25 C, +85 C VN = -0.5V -40 C
2.8 2.6 2.4 TA = -40 C, +25 C, +85 C
ERROR - dB (10mV/dB)
2.2
0C
+25 C VPDB - V
2.0 1.8 1.6 1.4 1.2 1.0 0.8
-40 C +25 C +85 C
1n
10n
100n
1 10 INPUT - A
100
1m
10m
0.6 0 1 2 3 4 5 6 INPUT - mA 7 8 9 10
TPC 2. Logarithmic Conformance (Linearity) for VLOG
TPC 5. VPDB vs. IPD
2.0
2.4
VP = 4.5V, 5.0V, 5.5V VN = -0.1V
1.25 TA = -40 C, +25 C, +85 C VP = 3.0V 1.00 0.75 -40 C 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 10m ERROR - dB (10mV/dB)
ERROR FROM IDEAL OUTPUT - dB (10mV/dB)
1.5 1.0 0.5 0 -0.5
2.2 2.0 1.8 VOUT - V
4.5V 5.0V 5.5V
1.6 1.4 +25 C 1.2 +85 C
-1.0 -1.5 -2.0 100p
1.0 0.8
1n 10n 100n 1 10 INPUT - A 100 1m 10m
0.6 100p
1n
10n
100n
1 10 INPUT - A
100
1m
TPC 3. Absolute Deviation from Nominal Specified Value of VLOG for Several Supply Voltages
TPC 6. Logarithmic Conformance (Linearity) for a 3 V Single Supply (See Figure 6)
-4-
REV. A
AD8304
10 0 NORMALIZED RESPONSE - dB 1nA -10 -20 -30 -40 -50 -60 -70 100 10mA 1mA 10nA100nA 1 A
10
10 A 100 A
WIDEBAND NOISE - mV rms
9 8 7 6 5 4 3 2 1
1k
10k 100k 1M FREQUENCY - Hz
10M
100M
0 1n
10n
100n
1 10 100 INPUT CURRENT - A
1m
10m
TPC 7. Small Signal AC Response, IPD to VLOG (5% Sine Modulation of IPD at Frequency)
TPC 10. Total Wideband Noise Voltage at VLOG vs. IPD
100 10kHz 100kHz 10
3 GAIN = 1 , 2 , 2.5 , 5
NORMALIZED RESPONSE - dB
0 AV = 5 -3 AV = 2.5 -6 AV = 2 AV = 1
V rms/ Hz
1 100Hz 1kHz 0.1 1MHz
-9
0.01 1n
10n
100n
1
10 IPD - A
100
1m
10m
-12 100
1k
10k 100k 1M FREQUENCY - Hz
10M
100M
TPC 8. Spot Noise Spectral Density at VLOG vs. IPD
TPC 11. Small Signal Response of Buffer
100 1nA
10
fC = 1kHz
0
NORMALIZED GAIN - dB
10 10nA
V rms/ Hz
-10 -20 -30 -40 -50 -60
1A 1 100nA 10 A >100 A 0.1
0.01 100
1k
10k 100k FREQUENCY - Hz
1M
10M
-70 10
100
1k FREQUENCY - Hz
10k
100k
TPC 9. Spot Noise Spectral Density at VLOG vs. Frequency
TPC 12. Small Signal Response of Buffer Operating as Two-Pole Filter
REV. A
-5-
AD8304
2.0 TA = 25 C 1.5 1.0 5 0.5 0 -0.5 -1.0 -20 -1.5 -2.0 100p -25 1n 10n 100n 1 10 INPUT - A 100 1m 10m -30 -40 -30 -20 -10 MEAN - 3
VREF DRIFT - mV
20 15 MEAN + 3 10
ERROR - dB (10mV/dB)
MEAN + 3
0 -5 -10 -15 MEAN - 3
0
10 20 30 40 50 TEMPERATURE - C
60
70
80
90
TPC 13. Logarithmic Conformance Error Distribution (3 to Either Side of Mean)
TPC 16. VREF Drift vs. Temperature (3 to Either Side of Mean)
5 TA = 0 C, 70 C
SLOPE CHANGE FROM 25 C - mV/dec
3 2 1 0 -1 -2 -3 -4 -5 -40 -30 -20 -10 MEAN - 3
4 3 ERROR - dB (10mV/dB) 2 MEAN + 3 @ 70 C 1 0 -1 -2 -3 -4 -5 100p 1n 10n 100n 1 10 INPUT - A 100 1m 10m MEAN 3 @0C MEAN - 3 @ 70 C
MEAN + 3
0
10 20 30 40 50 TEMPERATURE - C
60
70
80
90
TPC 14. Logarithmic Conformance Error Distribution (3 to Either Side of Mean)
TPC 17. Slope Drift vs. Temperature (3 to Either Side of Mean)
5 TA = 4 MEAN 3 ERROR - dB (10mV/dB) 2 1 0 -1 -2 -3 -4 -5 100p 1n 10n 100n 1 10 INPUT - A 100 1m 10m MEAN 3 @ 40 C MEAN 3 @ 85 C 3 @ 40 C 40 C, 85 C
40
INTERCEPT CHANGE FROM 25 C - pA
30 MEAN + 3 20 10 0 -10 -20 -30 -40 -50 -40 -30 -20 -10 MEAN - 3
0
10 20 30 40 50 TEMPERATURE - C
60
70
80
90
TPC 15. Logarithmic Conformance Error Distribution (3 to Either Side of Mean)
TPC 18. Intercept Drift vs. Temperature (3 to Either Side of Mean)
-6-
REV. A
AD8304
8 6 4
vOS DRIFT - mV
160 140 MEAN + 3 120 100
HITS
2 0
80 60
-2 MEAN - 3
40 20 0 60
-4
-6 -40 -30 -20 -10
0
10 20 30 40 50 TEMPERATURE - C
60
70
80
90
80 100 120 LOGARITHMIC INTERCEPT - pA
140
TPC 19. Output Buffer Offset vs. Temperature (3 to Either Side of Mean)
TPC 21. Distribution of Logarithmic Intercept, Sample 1000
180 160 140 120 HITS 100 80 60 40 20 0 196
180 160 140 120 HITS 198 200 202 LOGARITHMIC SLOPE - mV/dec 204 100 80 60 40 20 0 -20
-10 0 10 INPUT GUARD OFFSET - mV
20
TPC 20. Distribution of Logarithmic Slope, Sample 1000
TPC 22. Distribution of Input Guard Offset Voltage (VINPT - VSUM), Sample 1000
REV. A
-7-
AD8304
BASIC CONCEPTS Optical Measurements
The AD8304 uses an advanced circuit implementation that exploits the well known logarithmic relationship between the base-to-emitter voltage, VBE, and collector current, IC, in a bipolar transistor, which is the basis of the important class of translinear circuits*:
VBE = VT log( I C /I S )
(1)
When interpreting the current IPD in terms of optical power incident on a photodetector, it is necessary to be very clear about the transducer properties of a biased photodiode. The units of this transduction process are expressed as amps per watt. The parameter , called the photodiode responsivity, is often used for this purpose. For a typical InGaAs p-i-n photodiode, the responsivity is about 0.9 A/W. It is also important to note that amps and watts are not usually related in this proportional manner. In purely electrical circuits, a current IPD applied to a resistive load RL results in a power proportional to the square of the current (that is, IPD2 RL). The reason for the difference in scaling for a photodiode interface is that the current IPD flows in a diode biased to a fixed voltage, VPDB. In this case, the power dissipated within the detector diode is simply proportional to the current IPD (that is, IPDVPDB) and the proportionality of IPD to the optical power, POPT, is preserved.
There are two scaling quantities in this fundamental equation, namely the thermal voltage VT = kT/q and the saturation current IS. These are of key importance in determining the slope and intercept for this class of log amp. VT has a process-invariant value of 25.69 mV at T = 25C and varies in direct proportion to absolute temperature, while IS is very much a process- and device-dependent parameter, and is typically 10-16 A at T = 25C but exhibits a huge variation over the temperature range, by a factor of about a billion. While these variations pose challenges to the use of a transistor as an accurate measurement device, the remarkable matching and isothermal properties of the components in a monolithic process can be applied to reduce them to insignificant proportions, as will be shown. Logarithmic amplifiers based on this unique property of the bipolar transistor are called translinear log amps to distinguish them from other Analog Devices products designed for RF applications that use quite different principles. The very strong temperature variation of the saturation current IS is readily corrected using a second reference transistor, having an identical variation, to stabilize the intercept. Similarly, proprietary techniques are used to ensure that the logarithmic slope is temperature-stable. Using these principles in a carefully scaled design, the now accurate relationship between the input current, IPD, applied to Pin INPT, and the voltage appearing at the intermediate output Pin VLOG is:
I PD = POPT
(4)
Accordingly, a reciprocal correspondence can be stated between the intercept current, IZ, and an equivalent "intercept power," PZ, thus:
I Z = PZ
and Equation 2 may then be written as:
(5)
VLOG = VY log10( POPT /PZ )
(6)
For the AD8304 operating in its default mode, its IZ of 100 pA corresponds to a PZ of 110 picowatts, for a diode having a responsivity of 0.9 A/W. Thus, an optical power of 3 mW would generate:
VLOG = 0.2V log10 ( 3 mW /110 pW ) = 1.487 V
(7)
VLOG = VY log10( I PD /I Z )
(2)
VY is called the slope voltage (in the case of base-10 logarithms, it is also the "volts per decade"). The fixed current IZ is called the intercept. The scaling is chosen so that VY is trimmed to 200 mV/decade (10 mV/dB). The intercept is positioned at 100 pA; the output voltage VLOG would cross zero when IPD is of this value. However, when using a single supply the actual VLOG must always be slightly above ground. On the other hand, by using a negative supply, this voltage can actually cross zero at the intercept value. Using Equation 2, one can calculate the output for any value of IPD. Thus, for an input current of 25 nA,
Note that when using the AD8304 in optical applications, the interpretation of VLOG is in terms of the equivalent optical power, the logarithmic slope remains 10 mV/dB at this output. This can be a little confusing since a decibel change on the optical side has a different meaning than on the electrical side. In either case, the logarithmic slope can always be expressed in units of mV per decade to help eliminate any confusion.
Decibel Scaling
VLOG = 0.2 V log10(25 nA/100 pA) = 0.4796 V
(3)
In practice, both the slope and intercept may be altered, to either higher or lower values, without any significant loss of calibration accuracy, by using one or two external resistors, often in conjunction with the trimmed 2 V voltage reference at Pin VREF.
In cases where the power levels are already expressed as so many decibels above a reference level (in dBm, for a reference of 1 mW), the logarithmic conversion has already been performed, and the "log ratio" in the above expressions becomes a simple difference. One needs to be careful in assigning variable names here, because "P" is often used to denote actual power as well as this same power expressed in decibels, while clearly these are numerically different quantities. Such potential misunderstandings can be avoided by using "D" to denote decibel powers. The quantity VY ("volts per decade") must now be converted to its decibel value, VY = VY/10, because there are 10 dB per decade in the context of a power measurement. Then it can be stated that: VLOG = 20 ( DOPT - DZ ) mV /dB (8)
*For a basic discussion of the topic, see Translinear Circuits: An Historical Overview, B. Gilbert, Analog Integrated Circuits and Signal Processing, 9, pp. 95-118, 1996.
where DOPT is the optical power in decibels above a reference level, and DZ is the equivalent intercept power relative to the same level. This convention will be used throughout this data sheet.
-8-
REV. A
AD8304
To repeat the previous example: for a reference power level of 1 mW, a POPT of 3 mW would correspond to a DOPT of 10 log10(3) = 4.77 dBm, while the equivalent intercept power of 110 pW will correspond to a DZ of -69.6 dBm; now using Equation 8: VLOG = 20 mV {4.77 - (-69.9)} = 1.487 V (9) which is in agreement with the result from Equation 7.
GENERAL STRUCTURE
voltage is applied to a processing block--essentially an analog divider that effectively puts a variable proportional to temperature underneath the T in Equation 10. In this same block, IREF is transformed to the much smaller current IZ, to provide the previously defined value for VLOG, that is,
VLOG = VY log10 ( IPD /I Z )
(11)
The AD8304 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems, and will also be useful in many nonoptical applications. These notes explain the structure of this unique translinear log amp. Figure 1 is a simplified schematic showing the key elements.
VPDB 0.5V PHOTODIODE INPUT CURRENT ~10k IPD VSUM INPT 0.6V C1 0.5V Q1 R1 QM VBE1 Q2 VBE2 ACOM VNEG (NORMALLY GROUNDED) 5k 200 VBE1 VPDB VBE2- 296mVP IREF (INTERNAL) 0.5V VLOG VLOG INTERCEPT AND TEMPERATURE COMPENSATION (SUBTRACT AND DIVIDE BY T K) 40 A/dec
Recall that VY is 200 mV/decade and IZ is 100 pA. Internally, this is generated first as an output current of 40 A/decade (2 A/dB) applied to an internal load resistor from VLOG to ACOM that is laser-trimmed to 5 k 1%. The slope may be altered at this point by adding an external shunt resistor. This is required when using the minimum supply voltage of 3.0 V, because the span of VLOG for the full 160 dB (eight-decade) range of IPD amounts to 8 0.2 V = 1.6 V, which exceeds the internal headroom at this node. Using a shunt of 5 k, this is reduced to 800 mV, that is, the slope becomes 5 mV/dB. In those applications needing a higher slope, the buffer can provide voltage gain. For example, to raise the output swing to 2.4 V, which can be accommodated by the rail-to-rail buffer when using a 3.0 V supply, a gain of 3 can be used which raises the slope to 15 mV/dB. Slope variations implemented in these ways do not affect the intercept. Keep in mind these measures to address the limitations of a small positive supply voltage will not be needed when IPD is limited to about 1 mA maximum. They can also be avoided by using a negative supply that allows VLOG to run below ground, which will be discussed later. Figure 1 shows how a sample of the input current is derived using a very small monitoring transistor, QM, connected in parallel with Q1. This is used to generate the photodiode bias, VPDB, at Pin VPDB, which varies from 0.6 V when IPD = 100 pA, and reverse-biases the diode by 0.1 V (after subtracting the fixed 0.5 V at INPT) and rises to 2.6 V at IPD = 10 mA, for a net diode bias of 2 V. The driver for this output is current-limited to about 20 mA. The system is completed by the final buffer amplifier, which is essentially an uncommitted op amp with a rail-to-rail output capability, a 10 MHz bandwidth, and good load-driving capabilities, and may be used to implement multipole low-pass filters, and a voltage reference for internal use in controlling the scaling, but that is also made available at the 2.0 V level at Pin VREF. Figure 2 shows the ideal output VLOG versus IPD.
Bandwidth and Noise Considerations
Figure 1. Simplified Schematic
The photodiode current IPD is received at input Pin INPT. The summing voltage at this node is essentially equal to that on the two adjacent guard pins, VSUM, due to the low offset voltage of the ultralow bias J-FET op amp used to support the operation of the transistor Q1, which converts the current to a logarithmic voltage, as delineated in Equation 1. VSUM is needed to provide the collector-emitter bias for Q1, and is internally set to 0.5 V, using a quarter of the reference voltage of 2 V appearing on Pin VREF. In conventional translinear log amps, the summing node is generally held at ground potential, but that condition is not readily realized in a single-supply part. To address this, the AD8304 also supports the use of an optional negative supply voltage, VN, at Pin VNEG. For a VN of at least -0.5 V the summing node can be connected to ground potential. Larger negative voltages may be used, with essentially no effect on scaling, up to a maximum supply of 8 V between VPOS and VNEG. Note that the resistance at the VSUM pins is approximately 10 k to ground; this voltage is not intended as a general bias source. The input-dependent VBE of Q1 is compared with the fixed VBE of a second transistor, Q2, which operates at an accurate internally generated current, IREF = 10 A. The overall intercept is arranged to be 100,000 times smaller than IREF, in later parts of the signal chain. The difference between these two VBE values can be written as
VBE 1 - VBE 2 = kT /q log10 ( I PD /I REF )
(10)
Thus, the uncertain and temperature-dependent saturation current, IS that appears in Equation 1, has been eliminated. Next, to eliminate the temperature variation of kT/q, this difference REV. A -9-
The response time and wide-band noise of translinear log amps are fundamentally a function of the signal current IPD. The bandwidth becomes progressively lower as I PD is reduced, largely due to the effects of junction capacitances in Q1. This is easily understood by noting that the transconductance (gm) of a bipolar transistor is a linear function of collector current, IC, (hence, translinear), which in this case is just IPD. The corresponding incremental emitter resistance is: 1 kT re = = (12) gm qI PD Basically, this resistance and the capacitance CJ of the transistor generate a time constant of reCJ and thus a corresponding low-pass corner frequency of: qI PD f3dB = (13) 2 kTC j showing the proportionality of bandwidth to current.
AD8304
1.6
is thus 4.0 V, which can be accommodated by the rail-to-rail output stage when using the recommended 5 V supply. The capacitor from VLOG to ground forms an optional singlepole low-pass filter. Since the resistance at this pin is trimmed to 5 k, an accurate time constant can be realized. For example, with CFLT = 10 nF, the -3 dB corner frequency is 3.2 kHz. Such filtering is useful in minimizing the output noise, particularly when IPD is small. Multipole filters are more effective in reducing noise, and are discussed below. A capacitor between VSUM and ground is essential for minimizing the noise on this node. When the bias voltage at either VPDB or VREF is not needed these pins should be left unconnected.
Slope and Intercept Adjustments
1n 10n 100n 1 10 INPUT - A 100 1m 10m
1.2
VLOG - V
0.8
0.4
0 100p
Figure 2. Ideal Form of VLOG vs. IPD
Using a value of 0.3 pF for CJ evaluates to 20 MHz/mA. Therefore, the minimum bandwidth at IPD = 100 pA would be 2 kHz. While this simple model is useful in making a point, it excludes other effects that limit its usefulness. For example, the network R1, C1 in Figure 1, which is necessary to stabilize the system over the full range of currents, affects bandwidth at all values of IPD. Later signal processing blocks also limit the maximum value. TPC 7 shows ac response curves for the AD8304 at eight representative currents of 100 pA to 10 mA, using R1 = 750 and C1 = 1000 pF. The values for R1 and C1 ensure stability over the full 160 dB dynamic range. More optimal values may be used for smaller subranges. A certain amount of experimental trial and error may be necessary to select the optimum input network component values for a given application. Turning now to the noise performance of a translinear log amp, the relationship between IPD and the voltage noise spectral density, SNSD, associated with the VBE of Q1, evaluates to the following: SNSD = 14.7 IPD (14)
The choice of slope and intercept depends on the application. The versatility of the AD8304 permits optimal choices to be made in two common situations. First, it allows an input current range of less than the full 160 dB to use the available voltage span at the output. Second, it allows this output voltage range to be optimally positioned to fit the input capacity of a subsequent ADC. In special applications, very high slopes, such as 1 V/dec, allow small subranges of IPD to be covered at high sensitivity. The slope can be lowered without limit by the addition of a shunt resistor, RS, from VLOG to ground. Since the resistance at this pin is trimmed to 5 k, the accuracy of the modified slope will depend on the external resistor. It is calculated using:
VY = VY RS R'S +5 k
VP VPS2
10
(15)
PWDN
2
VPS1
12
IPD PDB VPDB NC
3 4
BIAS ~10k
VREF 0.5V VLOG
7
VREF 200mV/DEC CFLT
VSUM INPT 5k VSUM TEMPERATURE COMPENSATION BFIN BFNG
8 9 13
where SNSD is nV/Hz, IPD is expressed in microamps and TA = 25C. For an input of 1 nA, SNSD evaluates to almost 0.5 V/Hz; assuming a 20 kHz bandwidth at this current, the integrated noise voltage is 70 V rms. However, the calculation is not complete. The basic scaling of the VBE is approximately 3 mV/dB; translated to 10 mV/dB, the noise predicted by Equation 14 must be multiplied by approximately 3.33. The additive noise effects associated with the reference transistor, Q2, and the temperature compensation circuitry must also be included. The final voltage noise spectral density presented at the VLOG Pin varies inversely with IPD, but not as simple as square root. TPCS 8 and 9 show the measured noise spectral density versus frequency at the VLOG output, for the same nine-decade spaced values of IPD.
Chip Enable
C1 1nF 10nF R1 750
5
RB 10k
RA 15k VNEG
1
ACOM
14
VOUT
11
NC = NO CONNECT
VOUT 500mV/DEC
Figure 3. Basic Connections (RA, RB, CFLT are optional; R1 and C1 are the default values)
The AD8304 may be powered down by taking the PWDN Pin to a high logic level. The residual supply current in the disabled mode is typically 60 A.
USING THE AD8304
For example, using RS = 3 k, the slope is lowered to 75 mV per decade or 3.75 mV/dB. Table I provides a selection of suitable values for RS and the resulting slopes.
Table I. Examples of Lowering the Slope
The basic connections (Figure 3) include a 2.5:1 attenuator in the feedback path around the buffer. This increases the basic slope of 10 mV/dB at the VLOG Pin to 25 mV/dB at VOUT. For the full dynamic range of 160 dB (80 dB optical), the output swing -10-
RS (k ) 3 5 15
VY (mV/dec) 75 100 150 REV. A
AD8304
In addition to uses in filter and comparator functions, the buffer amplifier provides the means to adjust both the slope and intercept, which require a minimal number of external components. The high input impedance at BFIN, low input offset voltage, large output swing, and wide bandwidth of this amplifier permit numerous transformations of the basic VLOG signal, using standard op amp circuit practices. For example, it has been noted that to raise the gain of the buffer, and therefore the slope, a feedback attenuator, RA and RB in Figure 3, should be inserted between VLOG and the inverting input Pin BFNG. A wide range of gains may be used and the resistor magnitudes are not critical; their parallel sum should be about equal to the net source resistance at the noninverting input. When high gains are used, the output dynamic range will be reduced; for maximum swing of 4.8 V, it will amount to simply 4.8 V/VY decades. Thus, using a ratio of 3 , to set up a slope 30 mV/dB (600 mV/ decade), eight decades can be handled, while with a ratio of 5 , which sets up a slope of 50 mV/dB (1 V/decade), the dynamic range is 4.8 decades, or 96 dB. When using a lower positive supply voltage, the calculation proceeds in the same way, remembering to first subtract 0.2 V to allow for 0.1 V upper and lower headroom in the output swing. Alteration of the logarithmic intercept is only slightly more tricky. First note that it will rarely be necessary to lower the intercept below a value of 100 pA, since this merely raises all output voltages further above ground. However, where this is required, the first step is to raise the voltage VLOG by connecting a resistor, RZ, from VLOG to VREF (2 V) as shown in Figure 4.
VP VPS2 IPD PDB NC 6
3 4 10
Table II. Examples of Lowering the Intercept
VY (mV/decade) 200 200 200 300 300 300 400 400 400 500 500 500
IZ (pA) 1 10 50 1 10 50 1 10 50 1 10 50
RA (k ) 20.0 10.0 3.01 10.0 8.06 6.65 11.5 9.76 8.66 16.5 14.3 13.0
RB (k ) 100 100 100 12.4 12.4 12.4 8.2 8.2 8.2 8.2 8.2 8.2
RZ (k ) 25 50 165 25 50 165 25 50 165 25 50 165
Equations for use with Table II:
I RZ RLOG VOUT = G VY x x log10 PD + VREF x RZ + RLOG IZ RLOG + RZ where
G = 1+ RA and RLOG = 5 k RB
PWDN
2
VPS1
12
BIAS ~10k
VREF 0.5V VLOG
VREF
7
VPDB RZ VSUM INPT 5k VSUM TEMPERATURE COMPENSATION BFIN BFNG
8 9 13
Generally, it will be useful to raise the intercept. Keep in mind that this moves the VLOG line in Figure 2 to the right, lowering all output values. Figure 5 shows how this is achieved. The feedback resistors, RA and RB, around the buffer are now augmented with a third resistor, RZ, placed between the Pins BFNG and VREF. This raises the zero-signal voltage on BFNG, which has the effect of pushing VOUT lower. Note that the addition of this resistor also alters the feedback ratio. However, this is readily compensated in the design of the network. Table III lists the resistor values for representative intercepts.
Table III. Examples of Raising the Intercept
VY (mV/decade) 300 300 400 400 400 500 500 500
IZ (nA) 10 100 10 100 500 10 100 500
RA (k ) 7.5 8.25 10 9.76 9.76 12.4 12.4 11.5
RB (k ) 37.4 130 16.5 25.5 36.5 12.4 16.5 20.0
RC(k ) 24.9 18.2 25.5 16.2 13.3 24.9 16.5 12.4
C1 1nF 10nF R1 750
5
RA
1 14 11
RB
VNEG NC = NO CONNECT
ACOM
VOUT
VOUT
Figure 4. Method for Lowering the Intercept
This has the effect of elevating VLOG for small inputs while lowering the slope to some extent because of the shunt effect of RZ on the 5 k output resistance. Then, if necessary, the slope may be increased as before, using a feedback attenuator around the buffer. Table II lists some examples of lowering the intercept combined with various slope variations.
Equations for use with Table III: RA RB I VOUT = G VY x log10 PD - VREF x IZ RA RB + RC where
G = 1+ RA R x RB and RA RB = A RA + RB RB RC
REV. A
-11-
AD8304
VP VPS2 IPD PDB NC 6
3 4 10
Using the Adaptive Bias
PWDN
2
VPS1
12
BIAS ~10k
VREF 0.5V
VREF
7
VPDB VSUM VLOG INPT 5k VSUM TEMPERATURE COMPENSATION BFIN BFNG
8 9 13
RC
C1 1nF 10nF R1 750
5
RA
1 14 11
RB
VNEG NC = NO CONNECT
ACOM
VOUT
VOUT
For most photodiode applications, the placement of the anode somewhat above ground is acceptable, as long as the positive bias on the cathode is adequate to support the peak current for a particular diode, limited mainly by its series resistance. To address this matter, the AD8304 provides for the diode a bias that varies linearly with the current. This voltage appears at Pin VPDB, and varies from 0.6 V (reverse-biasing the diode by 0.1 V) for IPD = 100 pA and rises to 2.6 V (for a diode bias of 1 V) at IPD = 10 mA. This results in a constant internal junction bias of 0.1 V when the series resistance of the photodiode is 200 . For optical power measurements over a wide dynamic range the adaptive biasing function will be valuable in minimizing dark current while preventing the loss of photodiode bias at high currents. Use of the adaptive bias feature is shown in Figure 7.
VP VPS2
10
Figure 5. Method for Raising the Intercept
Low Supply Slope and Intercept Adjustment
PWDN
2
VPS1
12
When using the device with a positive supply less than 4 V, it is necessary to reduce the slope and intercept at the VLOG Pin in order to preserve good log conformance over the entire 160 dB operating range. The voltage at the VLOG Pin is generated by an internal current source with an output current of 40 A/decade feeding the internal laser-trimmed output resistance of 5 k. When the voltage at the VLOG Pin exceeds VP - 2.3 V, the current source ceases to respond linearly to logarithmic increases in current. This headroom issue can be avoided by reducing the logarithmic slope and intercept at the VLOG Pin. This is accomplished by connecting an external resistor RS from the VLOG Pin to ground in combination with an intercept lowering resistor RZ. The values shown in Figure 6 illustrate a good solution for a 3.0 V positive supply. The resulting logarithmic slope measured at VLOG is 62.5 mV/decade with a new intercept of 57 fA. The original logarithmic slope of 200 mV/decade can be recovered using voltage gain on the internal buffer amplifier.
VP VPS2 IPD PDB NC 6
3 4 10
CPB VPDB
6
PDB ~10k VSUM
BIAS
VREF 0.5V VLOG
7 VREF
IPD
3 4
CFILT
8
INPT 5k VSUM TEMPERATURE COMPENSATION BFIN BFNG
C1 1nF 10nF R1 750
9
5
RB
13
RA
1 14 11
VNEG
ACOM
VOUT
VOUT
Figure 7. Using the Adaptive Biasing
PWDN
2
VPS1
12
BIAS ~10k
VREF 0.5V
VREF
7
Capacitor CPB, between the photodiode cathode at Pin VPDB and ground, is included to lower the impedance at this node and thereby improve the high frequency accuracy at those current levels where the AD8304 bandwidth is high. It also ensures an HF path for any high frequency modulation on the optical signal which might not otherwise be accurately averaged. It will not be necessary in all cases, and experimentation may be required to find an optimum value.
Changing the Voltage at the Summing Node
VPDB VSUM VLOG INPT 5k VSUM TEMPERATURE COMPENSATION BFIN BFNG
8 9
RZ 15.4k RS 2.67k
C1 1nF 10nF R1 750
5
62.5mV/DEC
13
RA 4.98k
1 14 11
RB 2.26k
VNEG NC = NO CONNECT
ACOM
VOUT
VOUT
The default value of VSUM is determined by using a quarter of VREF (2 V). This may be altered by applying an independent voltage source to VSUM, or by adding an external resistive divider from VREF to VSUM. This network will operate in parallel with the internal divider (40 k and 13.3 k), and the choice of external resistors should take this into account. In practice, the total resistance of the added string may be as low as 10 k (consuming 400 A from VREF). Low values of VSUM and thus VCE (see Figure 13) are not advised when large values of IPD are expected.
Implementing Low-Pass Filters
Figure 6. Recommended Low Supply Application Circuit
Noise, leading to uncertainty in an observed value, is inherent to all measurement systems. Translinear log amps exhibit significant amounts of noise for reasons stated above, and are more troublesome at low current levels. The standard way of addressing this problem is to average the measurement over an appropriate time interval. This can be achieved in the digital domain, in post-ADC DSP, or in analog form using a variety of low-pass structures.
-12-
REV. A
AD8304
The use of a capacitor at the VLOG Pin to create a single-pole filter has already been mentioned. The small added cost of the few external components needed to realize a multipole filter is often justified in a high performance measurement system. Figure 8 shows a Sallen-Key filter structure. Here, the resistor needed at the front of the network is provided entirely by the accurate 5 k present at the VLOG output; RB will have a similar value. The corner frequency and Q (damping factor) are determined by the capacitors CA and CB and the gain G = (RA + RB)/RB. A suggested starting point for choosing these components using various gains is provided in Table IV; the values shown are for a 1 kHz corner (also see TPC 12). This frequency can be increased or decreased by scaling the capacitor values. Note that RD, G, and the capacitor ratio CA/CB should not deviate from the suggested values to maintain the shape of the ac amplitude response and pulse overshoot provided by the values shown in this table. In all cases, the roll-off rate above the corner is 40 dB/dec.
VP VPS2 IPD PDB NC 6
3 4 10
VP VPS2 IPD PDB NC 6
3 4 10
PWDN
2
VPS1
12
BIAS ~10k
VREF 0.5V
7
VREF
VPDB VSUM INPT 5k VSUM TEMPERATURE COMPENSATION BFIN BFNG
8 9 13
VLOG RG
C1 1nF 10nF R1 750
5
RA RH
VNEG NC = NO CONNECT
1
ACOM
14
VOUT
11
VOUT
Figure 9. Using the Buffer as a Comparator
Using a Negative Supply
PWDN
2
VPS1
12
Most applications of the AD8304 will require only a single supply of 3.0 V to 5.5 V. However, to provide further versatility, dual supplies may be employed, as illustrated in Figure 10. The use of a negative supply, VN, allows the summing node to be placed exactly at ground level, because the input transistor (Q1 in Figure 1) will have a negative bias on its emitter. VN may be as small as -0.5 V, making the VCE the same as for the default case. This bias need not be accurate, and a poorly defined source can be used.
RB CA RA CB
BIAS ~10k
VREF 0.5V
7
VREF
VPDB VSUM INPT 5k VSUM TEMPERATURE COMPENSATION BFIN BFNG
8 9 13
VLOG RD
C1 1nF 10nF R1 750k
5
VNEG NC = NO CONNECT
1
ACOM
14
11
VOUT
VOUT
Figure 8. Two-Pole Low-Pass Filter
Table IV. Two-Pole Filter Parameters for 1 kHz Cutoff Frequency*
A larger supply of up to -5 V may be used. The effect on scaling is minor. It merely moves the intercept by ~0.01 dB/V. Accordingly, an uncertainty of 0.2 V in VN would result in a negligible error of 0.002 dB. The slope is unaffected by VN. The log linearity will be degraded at the extremes of the dynamic range as indicated in Figure 11. The bias current, buffer output (and its load) current, and the full IPD all have to be absorbed by this negative supply, and its supply capacity must be ensured for the maximum current condition.
VP
RA (k ) 0 10 12 24
RB (k ) open 10 8 6
G 1 2 2.5 5
VY (V/decade) 0.2 0.4 0.5 1.0
RD (k ) 11.3 6.02 12.1 10.0
CA (nF) 12 33 33 33
CB (nF) 12 22 18 18
VPS2 IPD
10
PWDN
2
VPS1
12
PDB NC 6
3 4
BIAS ~10k
VREF 0.5V
7
VREF
VPDB VSUM INPT 5k VSUM TEMPERATURE COMPENSATION BFIN BFNG
8 9 13
VLOG
The corner frequency can be adjusted by scaling capacitors C A and CB. For example, to reduce the corner frequency to 100 Hz, raise the values of C A and CB by 10 . *See TPC 12.
C1 1nF R1 750
5
RA
Operation in Comparator Modes
RB
1
In certain applications, the need may arise to generate a logical output when the input current has reached a certain value. This can be easily addressed by using a fraction of the voltage reference to provide the setpoint (threshold) and using the buffer without feedback in a comparator mode, as illustrated in Figure 9. Since VLOG runs from ground up to 1.6 V maximum, the 2 V reference is more than adequate to cover the full dynamic range of IPD. Note that the threshold for an increasing IPD is unchanged, while the release point for decreasing currents is 5 dB below this. Raising RH to 5 M reduces the hysteresis to 0.5 dB, or it may be increased using a lower value for RH.
NC = NO CONNECT
VNEG
ACOM
14
VOUT
11
VOUT
VN (-0.5V TO -3V)
Figure 10. Using a Negative Supply
With the summing node at ground, the AD8304 may now be used as a voltage-input log amp, simply by inserting a suitably scaled resistor from the voltage source to the INPT Pin. The logarithmic accuracy for small voltages is limited by the offset of the JFET op amp, appearing between this pin and VSUM. The use of a negative supply also allows the output to swing below ground, thereby allowing the intercept to correspond to a midrange value of IPD. However, the voltage VLOG remains referenced to the -13-
REV. A
AD8304
ACOM Pin, and does not normally go negative with regard to this pin, but is free to do so. Therefore, a resistor from VLOG to the negative supply can lower VLOG, thus raising the intercept. A more accurate method for repositioning the intercept is described below.
2.0 1.5 1.0 WITHOUT INTERCEPT ADJUST 0.5 0 -0.5 WITH INTERCEPT ADJUST -1.0 -1.5 VNEG = -3 -2.0 100p 1n 10n 100n 1 10 INPUT - A 100 1m 10m VNEG = -0.5 VNEG = 0
APPLICATIONS
The AD8304 incorporates features that improve its usefulness in both fiber optic supervisory applications and in more general ones. To aid in the exploration of these possibilities, a SPICE macromodel is provided and a versatile evaluation board is available. The macromodel is shown in generalized schematic form (and thus is independent of variations in SPICE programs) in Figure 12. Q1, QM, and Q2 (here made equal in size) correspond to the identical transistors in Figure 1. The model parameters for these transistors are not critical; the default model provided in SPICE libraries will be satisfactory. However, the AD8304 employs compensation techniques to reduce errors caused by junction resistances (notably, RB and RE) at high input currents. Therefore, it is advisable to set these to zero. While this will not model the AD8304 precisely, it is safer than using possibly high default values for these parameters. The low current model parameters may also need consideration. Note that no attempt is made to capture either dynamic behavior or the effects of temperature in this simple macromodel; scaling is correct for 27C.
ERROR - dB (10mV/dB)
Figure 11. Log Conformance (Linearity) vs. IPD for Various Negative Supplies
E2
5
V1 V IN I1 IPD C1
+
1 3k 2
I1
I2 4 E3 6
E4 7 100k V2 R1 + V C2 R2 VLOG RL
3
Q1
Q2
Q3
I1 C1 E1 V1 Q1 I2 Q2 I3 Q3 .MODEL E2 E3 E4 V2 R1 C2 R2 RL
0 IN 2 1 IN 0 3 0 4 NPN 5 6 7 8 8 9 9 VLOG
IN 0 0 0 2 3 3 4 4 NPN 0 0 0 7 9 0 VLOG 0
DC 1.0N IN 0.5 0 1 0 316.2 0
1A 1 NPN NPN NPN 3K
POLY (2) 2 3 1 0 0, 0, 0, 0, 1 POLY (2) 4 3 7 0 0, 0, 0, 0, 1 6 5 100K 0.8 100 163P 4.9K 1000K
Figure 12. Basic Macromodel
-14-
REV. A
AD8304
Summing Node at Ground and Voltage Inputs
A negative supply may be used to reposition the input node at ground potential. A voltage as small as -0.5 V is sufficient. Figure 13 shows the use of this feature. An input current of up to 10 mA is supported. This connection mode will be useful in cases where the source is a positive voltage VSIG referenced to ground, rather than for use with photodiodes, or other "perfect" current sources. RIN scales the input current and should be chosen to optimally position the range of IPD, or provide a very high input resistance, thus minimizing the loading of the signal source. For example, assume a voltage source that spans the four-decade range from 100 mV to 1 kV and is desired to maximize RIN. When set to 1 G, IPD spans the range 100 pA to 1 mA. Using a value of 10 M, the same four decades of input voltage would span the central current range of 10 nA to 100 mA. Smaller input voltages can be measured accurately when aided by a small offset-nulling voltage applied to VSUM. The optional network shown in Figure 13 provides more than 20 mV for this purpose.
VP VPS2
10
is grounded. A negative supply capable of supporting the input current IPD must be used, the fraction of quiescent bias that flows out of the VNEG Pin, and the load current at VLOG. For the example shown in Figure 14, this totals less than 20 mA when driving a 1 k load as far as -4 V. The use of a much larger value for the intercept may be useful in certain situations. In this example, it has been moved up four decades, from the default value of 100 pA to the center of the full eight-decade range at 1 mA. Using a voltage input as described above, this corresponds to an altered voltage-mode intercept, VZ, which would be 1 V for RIN = 1 M. To take full advantage of the larger output swing, the gain of the buffer has been increased to 4.53, resulting in a scaling of 900 mV/decade and a full-scale output of 3.6 V.
VP VPS2
10
PWDN
2
VPS1
12
AD8304
PDB NC 6
3
BIAS ~10k
VREF 0.5V
7
VREF
VPDB VSUM VLOG INPT 5k VSUM TEMPERATURE COMPENSATION BFIN BFNG
8 9 13
RIN
4
PWDN
2
VPS1
12
AD8304
PDB NC VPDB
6 3
IPD VSIG
5
RC 12.4k
BIAS ~10k
VREF 0.5V
7 VREF
RA 13.3k 1k RB 22.6k
1 14 11
VSUM INPT 5k VSUM TEMPERATURE COMPENSATION BFIN BFNG
8 9 13
VLOG
RIN
4
IPD VSIG
5
VP
VLOW 10k NC = NO CONNECT
VNEG VN
ACOM
VOUT
VOUT RL 1k
RA 1k RB
1 14 11
Figure 14. Using a Negative Supply to Allow the Output to Swing Below Ground
Inverting the Slope
VP
VLOW 10k
VNEG VN
ACOM
VOUT
VOUT
NC = NO CONNECT
Figure 13. Using a Negative Supply and Placing VSUM at Ground Permits Voltage-Mode Inputs
The minimum voltage that can be accurately measured is then limited only by the drift in the input offset of the AD8304. The specifications show the maximum spread over the full temperature and supply range. Over a limited temperature range, and with a regulated supply, the offset drift will be lower; in this situation, processing of inputs down to 5 mV is practicable. The input system of the AD8304 is quasi-differential, so VSUM can be placed at an arbitrary reference level VLOW, over a wide range, and used as the "signal LO" of the source. For example, using VP = 5 V and VN = -3 V, VLOW can be any voltage within a 2.5 V range.
Providing Negative Outputs and Rescaling
The buffer is essentially an uncommitted op amp that can be used to support the operation of the AD8304 in a variety of ways. It can be completely disconnected from the signal chain when not needed. Figure 15 shows its use as an inverting amplifier; this changes the polarity of the slope. The output can either be repositioned to all positive values by applying a fraction of VREF to the BFIN Pin, or range negative when using a negative supply. The full design for a practical application is left undefined in this brief illustration, but a few cases will be discussed. For example, suppose we need a slope of -30 mV/dB; this requires the gain to be three. Since VLOG exhibits a source resistance of 5 k, RB must be 15 k. In cases where a small negative supply is available, the output voltage can swing below ground, and the BFIN Pin may be grounded. But a negative slope is still possible when only a single supply is used; a positive offset, VOFS, is applied to this pin, as indicated in Figure 15. In general, the resulting output voltage can be expressed as:
As noted, the AD8304 allows the buffer to drive a load to negative voltages with respect to ACOM, the analog common pin, which
R I VOUT = - B VY x log10 PD + VOFS 5 k IZ
(16)
REV. A
-15-
AD8304
VP VPS2 IPD
10
PWDN
2
VPS1
12
AD8304
PDB NC 6
3 4
BIAS ~10k
VREF 0.5V
7
VREF
VPDB VSUM INPT 5k VSUM TEMPERATURE COMPENSATION BFIN BFNG
8
down by 1.6 V. Clearly, a higher slope (or gain) is desirable, in which case VOFS should be set to a smaller voltage to avoid railing the output at low currents. If VOFS = 1.2 V and G = 33, VOUT now starts at 4.8 V and falls through this same voltage toward ground with a slope of -0.6 V per decade, spanning the full range of IPD.
Programmable Level Comparator with Hysteresis
VLOG VOFS
C1 1nF 10nF R1 750
9 13
5
RB
1 14 11
NC = NO CONNECT
VNEG
ACOM
VOUT VOUT
VN (-0.5V TO -3V)
Figure 15. Using the Buffer to Invert the Polarity of the Slope
The buffer amplifier and reference voltage permit a calibrated level detector to be realized. Figure 16 shows the use of a 10-bit MDAC to control the setpoint to within 0.1 dB of an exact value over the 100 dB range of 1 nA IPD 100 A when the fullscale output of the MDAC is equal to that of its reference. The 2 V VREF also sets the minimum value of VSPT to 0.2 V, corresponding to an input of 1 nA. Since 100 dB at the VLOG interface corresponds to a 1 V span, the resistor network is calculated to provide a maximum VSPT of 1.2 V while adding the required 10% of VREF. In this example, the hysteresis range is arranged to be 0.1 dB, (1 mV at VLOG) when using a 5 V supply. This will usually be adequate to prevent noise that causes the comparator output to thrash. That risk can be reduced further by using a low-pass filtering capacitor at VLOG (shown dotted) to decrease the noise bandwidth.
VP
When the gain is set to 13 (RB = 5 k) the 2 V VREF can be tied directly to BFIN, in which case the starting point for the output response is at 4 V. However, since the slope in this case is only -0.2 V/decade, the full current range will only take the output
VPS2
10
PWDN
2
VPS1
12
IPD
AD8304
PDB NC 6
3 4
BIAS ~10k
VREF 0.5V VLOG
VREF
7
VPDB VSUM INPT 5k VSUM TEMPERATURE COMPENSATION BFIN BFNG
8 9
1nF 10nF 750
5
VREF VOUT MDAC 49.9k 100k RH 50M VOUT VSPT
13
1
14
11
NC = NO CONNECT
VNEG
ACOM
VOUT
Figure 16. Calibrated Level Comparator
VP VPS2
10
PWDN
2
VPS1
12
AD8304
ISRC NC 6
3 4
PDB VPDB ~10k VSUM INPT
BIAS
VREF 0.5V
7
VREF
8
VLOG VREF VOUT MDAC
5k VSUM TEMPERATURE COMPENSATION
BFIN BFNG
25k
9 13
5
C1 10nF
1 14 11
100k
VNEG 1k C2 1nF VN (-0.5V TO -5V)
ACOM
VOUT
NC = NO CONNECT
Figure 17. Multidecade Current Source
-16-
REV. A
AD8304
Programmable Multidecade Current Source
The AD8304 supports a wide variety of general (nonoptical) applications. For example, the need frequently arises in test equipment to provide an accurate current that can be varied over many decades. This can be achieved using a logarithmic amplifier as the measuring device in an inverse function loop, as illustrated in Figure 16. This circuit generates the current:
TRIAX CONNECTOR* PWDN VNEG VPOS VOUT
AD8304
KEITHLEY 236 INPT CHARACTERIZATION BOARD VSUM VPDB VREF RIBBON CABLE BFIN VLOG *SIGNAL: INPT; GUARD: VSUM; SHIELD: GROUND
ISRC = 100 pA x 10 (
V SPT /0.2 )
(17)
The principle is as follows. The current in QA is forced to supply a certain IPD by measuring the error between a setpoint VSPT and VLOG, and nulling this error by integration. This is performed by the internal op amp and capacitor C1, with a time constant formed with the internal 5 k resistor. The choice of C1 in this example ensures loop stability over the full eight-decade range of output currents; C2 reduces phase lag. The system is completed with a 10-bit MDAC using VREF as its reference, whose output is scaled to 1.6 V FS by R1 and R2 (whose parallel sum is also 5 k). Transistor QA may be a single bipolar device, which will result in a small alpha error in ISRC (the current is monitored in the emitter branch), or a Darlington pair or an MOS device, either of which ensure a negligible difference between IPD and ISRC. In this example, the bipolar pair is used. The output voltage compliance is determined by the collector breakdown voltage of these transistors, while the minimum voltage depends on where VSUM is placed. Optional components could be added to put this node and VNEG at a low enough bias to allow the voltage to go slightly below ground. Many variations of this basic circuit are possible. For example, the current can be continuously controlled by a simple voltage, or by a second current. Larger output currents can be controlled by setting VSUM to zero and using a current shunt divider.
Characterization Setups and Methods
DC MATRIX, DC SUPPLIES, DMM
Figure 18. Primary Characterization Setup
The primary characterization setup shown in Figure 18 is used to measure the static performance, logarithmic conformance, slope and intercept, buffer offset and VREF drift with temperature, and the performance of the VPDB Pin functions. For the dynamic tests, such as noise and bandwidth, more specialized setups are used.
HP 3577A NETWORK ANALYZER OUTPUT INPUT INPUTA INPUTB
AD8304
+IN
AD8138
B POWER SPLITTER
1 VNEG 2 PWDN 3 VSUM 4 INPT 5 VSUM 6 VPDB 7 VREF
ACOM 14 BFNG 13 VPS1 12 VOUT 11 VPS2 10 BFIN VLOG
9 8
EVALUATION A BOARD
+VS 0.1 F
During the primary characterization of the AD8304, the device was treated as a high precision current-in logarithmic amplifier (converter). Rather than attempting to accurately generate photocurrents by illuminating a photodiode, precision current sources, like the Keithley 236, were used as input sources. Great care was taken when applying the low level input currents. The triax output of the current source was used with the guard connected to VSUM at the characterization board. On the board the input trace was guarded by connecting adjacent traces and a portion of an internal copper layer to the VSUM Pins. One obvious reason for the care was leakage current. With 0.5 V as the nominal bias on the INPT Pin, a resistance of 50 G to ground would cause 10 pA of leakage, or about one decibel of error at the low end of the measurement range. Additionally, the high output resistance of the current source and the long signal cable lengths commonly needed in characterization make a good receiver for 60 Hz emissions. Good guarding techniques help to reduce the pickup of unwanted signals.
49.9
Figure 19. Configuration for Buffer Amplifier Bandwidth Measurement
Figure 19 shows the configuration used to measure the buffer amplifier bandwidth. The AD8138 Evaluation Board provides a dc offset at the buffer input, allowing measurement in single-supply mode. The network analyzer input impedance was set to 1 M.
REV. A
-17-
AD8304
HP 3577A NETWORK ANALYZER OUTPUT INPUT INPUTA INPUTB
HP 89410A CHANNEL CHANNEL 2 1 SOURCE TRIGGER
POWER SPLITTER
AD8304
AD8304
1 VNEG
1 2 3
VNEG PWDN VSUM INPT VSUM VPDB VREF
ACOM 14 BFNG 13 VPS1 12 VOUT 11 VPS2 10 BFIN 9 VLOG 8 ALKALINE D CELL
ACOM 14 BFNG 13 VPS1 12 VOUT 11 VPS2 10 BFIN VLOG
9 8
+IN
2 PWDN
AD8138
B R1
3 VSUM 4 INPT
+VS 0.1 F
ALKALINE D CELL
R1
4 5 6
EVALUATION A BOARD
750 1nF
750 1nF
5 VSUM 6 VPDB 7 VREF
7
Figure 20. Configuration for Logarithmic Amplifier Bandwidth Measurement
Figure 21. Configuration for Noise Spectral Density Measurement
Evaluation Board
The setup shown in Figure 20 was used for frequency response measurements of the logarithmic amplifier section. In this configuration, the AD8138 output was offset to 1.5 V and R1 was adjusted to provide the appropriate operating current. The buffer amplifier was then used; still any capacitance added at the VLOG Pin during measurement would form a filter with the on-chip 5 k resistor. The configuration illustrated in Figure 21 measures the device noise. Batteries provide both the supply and the input signal to remove the supplies as a possible noise source and to reduce ground loop effects. The AD8304 Evaluation Board and the current setting resistors are mounted in closed aluminum enclosures to provide additional shielding to external noise sources.
An evaluation board is available for the AD8304, the schematic for which is shown in Figure 22, and the two board sides are shown in Figure 23 and Figure 24. It can be configured for a wide variety of experiments. The board is factory set for Photoconductive Mode with a buffer gain of unity, providing a slope of 10 mV/dB and an intercept of 100 pA. By substituting resistor and capacitor values, all of the application circuits presented in this data sheet can be evaluated. Table V describes the various configuration options.
+VS
GND
-VS
R10 10k
AD8304
C1 0.1nF R7 OPEN C2 1nF R5 OPEN
3 VSUM 1 VNEG
ACOM 14 BFNG 13 VPS1 12 VOUT 11 VPS2 10 R11 0 BFIN 9 VLOG 8 R14 0 C6 OPEN C5 OPEN C7 OPEN R1 OPEN R2 0 C3 1nF C4 0.1 F R13 0 R12 OPEN BUFFER OUT C8 OPEN LOG OUT
2 PWDN
SW1
LK2 OPEN INPUT LK1 INSTALLED R15 750 C11 1nF C10 0.1 F
R7 OPEN R9 0.1 F R6 OPEN
4 INPT
5 VSUM
6 VPDB
BIASER
C9 10nF
7 VREF
R4 OPEN R3 OPEN
Figure 22. Evaluation Board Schematic
-18-
REV. A
AD8304
Figure 23. Component Side Layout
Figure 24. Component Side Silkscreen
Table V. Evaluation Board Configuration Options Component VP, VN, AGND SW1, R10 R1, R2 Function Positive and Negative Supply and Ground Pins Device Enable: When SW1 is in the "0" position, the PWDN Pin is connected to ground and the AD8304 is in its normal operating mode. Buffer Amplifier Gain/Slope Adjustment: The logarithmic slope of the AD8304 can be altered using the buffer's gain-setting resistors, R1 and R2. Intercept Adjustment: A dc offset can be applied to the input terminals of the buffer amplifier to adjust the effective logarithmic intercept. Bias Adjustment: The voltage on the VSUM and INPT Pins can be altered using appropriate resistor values. R9 is populated with a decoupling capacitor to reduce noise pickup. The decoupling capacitor can be removed when a fixed bias is applied to VSUM. Supply Decoupling Capacitors Default Condition Not Applicable SW1 = Installed R10 = 10 k (Size 0603) R1 = Open (Size 0603) R2 = 0 (Size 0603) R3 = Open (Size 0603) R4 = Open (Size 0603) R5 = R6 = Open (Size 0603) R7 = R8 = Open (Size 0603) R9 = 0.1 F (Size 0603) C1 = C4 = 0.1 F (Size 0603) C2 = C3 = 1 nF (Size 0603) C9 = 10 nF (Size 0603) C10 = 0.1 F (Size 0603) R11 = R13 = 0 (Size 0603) R12 = Open (Size 0603) R14 = 0 (Size 0603) C5 = C6 = Open (Size 0603) C7 = C8 = Open (Size 0603) R15 = 750 (Size 0603) C11 = 1 nF (Size 0603) LK1 = Installed LK2 = Open
R3, R4 R5, R6, R7, R8, R9
C1, C2, C3, C4, C9
C10
Photodiode Biaser Decoupling: Provides high frequency decoupling of the adaptive bias output at Pin VPDB.
C5, C6, C7, C8, R11, Output Filtering: Allows implementation of a variety of filter configR12, R13, R14 urations, from simple RC low-pass filters to three-pole Sallen and Key.
R15, C11 LK1, LK2
Input Filtering: Provides essential HF compensation at the input Pin INPT. Guard/Shield Options: The shells of the SMA connectors used for the input and the photodiode bias can be set to the voltage on the VSUM Pin or connected to ground.
REV. A
-19-
AD8304
OUTLINE DIMENSIONS 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)
Dimensions shown in millimeters
5.10 5.00 4.90
14
8
4.50 4.40 4.30
1 7
6.40 BSC
PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 SEATING PLANE
0.20 0.09 8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Revision History
Location 8/02--Data Sheet changed from REV. 0 to REV. A. Page
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 New TPC 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to TPC 7 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to TPC 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Edits to USING THE AD8304 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edits to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edits to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 New Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Changes to Figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Changes to Table V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
-20-
REV. A
PRINTED IN U.S.A.
C02743-0-8/02(A)

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